Product Engineer - Tessent Design for Test (DFT)

Siemens EDA is a global technology leader in electronic design automation software. They are seeking a Product Engineer specializing in design-for-test (DFT) and test delivery at chip and system level to define new product capabilities, collaborate with R&D, and support product adoption and growth.

Responsibilities

• Define and characterize new product capabilities needed to meet customer requirements
• Work collaboratively with Tessent R&D to prototype, evaluate, and test new products and features within complex IC design flows
• Lead beta programs and support beta partners
• Drive product adoption and growth
• Create and deliver in-depth technical presentations, develop training material, white papers, contributed articles, and application notes
• Develop and review tool documentation such as user and reference manuals
• Work with customers as well as Siemens EDA stakeholders such as regional application engineers, global support engineers, and marketing
• Work through complex technical issues and independently create solutions and new methodologies
• Present complex principles in simple terms to broad audiences
• Collaborate and share information across team boundaries in written and spoken forms
• Some travel, domestic and international

Skills

• BS degree (or equivalent) in Electrical Engineering, Computer Science, Computer Engineering, or related field is required
• Candidate should be high energy, curious individual, self-motivated to learn new DFT methodologies and technologies
• Able to work as individual contributor
• Strong problem-solving, reasoning and deduction skills and the ability to analyze and debug complex design and simulation issues
• Proficiency in LINUX and Windows environments
• Proficiency in a scripting language like TCL (preferred) or Python
• Excellent written and spoken English language communication skills
• Excellent organizational skills
• Work location is Wilsonville, OR
• 1+ years of work experience, including DFT for complex ASICs / SOCs, including some of the following areas: Automatic test pattern generation (ATPG), internal scan, embedded scan compression (EDT), packetized test delivery (SSN), memory built-in self-test (MBIST), logic built-in self-test (LBIST), IEEE 1687 IJTAG, analog design and simulation, hierarchical DFT implementation
• Experience working with DFT tools, preferably Tessent tool suite
• Industry experience with inserting scan, running ATPG and debugging fault coverage
• Knowledge of IC design trends and emerging requirements
• Exposure to one or more adjacent IC disciplines such as the following a plus: RTL coding and verification using Verilog/SystemVerilog/VHDL, Synthesis and timing analysis, Place and route, Advanced IC packaging, DFT and test for embedded IP cores, Failure diagnosis, ATE use / test program development

Benefits

• Flexibility - Choosing between working at home and the office at other times is the norm here.
• Great benefits and rewards

Company Overview